01
TPU Specifications
Compare performance, memory, and interconnect across 7 generations
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02
Chip Architecture Diagrams
MXU, VPU, SPU, VMEM, HBM, and ICI organization per generation
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03
MXU (Matrix Multiply Unit) Internals
Systolic array architecture, weight-stationary dataflow, and pipelining
MXU PE (BF16 MAC)
VPU Lane (SIMD)
SPU (Scalar)
VMEM (SRAM)
HBM Stack
ICI Link
04
Deep Technical Architecture
Full stack: JAX → XLA → HLO → libtpu → Driver → Hardware