✓ Shipping Q2 2025

D-MATRIX

CORSAIR // Digital In-Memory Compute

Breaking through the memory wall with compute inside memory. D-Matrix's DIMC architecture integrates multipliers directly into memory cells, achieving 150 TB/s bandwidth—far beyond what HBM can deliver. The result: energy-efficient inference that makes generative AI commercially viable at scale.

2.4 PFLOPS
INT8 Compute
150 TB/s
Memory Bandwidth
256 GB
LPDDR5 Capacity
38 TOPS/W
Energy Efficiency
DIMC
CHIPLET
DIMC
CHIPLET
DIMC
CHIPLET
DIMC
CHIPLET
DIGITAL IN-MEMORY COMPUTE
COMPUTE INSIDE THE MEMORY

DIMC Architecture

Digital In-Memory Compute

The fundamental innovation: integrate multipliers directly into memory bit cells. Instead of moving data to compute units, computation happens where data lives. This eliminates the memory bandwidth bottleneck that constrains all conventional architectures.

Microscaling (MX) Formats

First to natively support OCP Microscaling formats (MXINT4, MXINT8, MXINT16). Block floating point with shared exponents reduces data movement while maintaining accuracy. Same formats adopted by NVIDIA Blackwell and Microsoft Maia.

Chiplet Architecture

Four chiplets per package on TSMC 6nm. Each chiplet contains DIMC cores with 2GB total SRAM. Two packages per PCIe card. Cards can be bridged via DMX Bridge for 16-chiplet clusters.

Two Operating Modes

SRAM mode: models stored in 2GB on-chip memory for maximum speed. LPDDR mode: access 256GB capacity at 400GB/s for larger models. Single card can fit two Llama3-70B models in MXINT8.

Corsair Specifications

TSMC 6nm
Process
4 Chiplets
Per Package
2 GB
On-Chip SRAM
256 GB
LPDDR5
9.6 PFLOPS
MXINT4
2.4 PFLOPS
MXINT8
PCIe 5.0
Interface
275-550W
TDP Range

Strategic Analysis

✦ Advantages

  • 150 TB/s memory bandwidth—far beyond HBM capabilities
  • 38 TOPS/W efficiency for power-constrained data centers
  • MX formats gaining industry adoption
  • Shipping product (Q2 2025) vs. competitors still in development
  • Supermicro and GigaIO partnerships for go-to-market
  • Microsoft M12 investment validates enterprise potential

⚠ Risks

  • No IEEE floating point support limits flexibility
  • LPDDR5 mode significantly slower than SRAM mode
  • Less funding/visibility than Groq, Cerebras
  • MX format ecosystem still maturing
  • Enterprise AI inference market highly competitive
  • Newer architecture with limited production track record