GRAPHCORE
IPU // Intelligence Processing Unit
The British challenger to NVIDIA. Founded in 2016, Graphcore pioneered the concept of "intelligence processing units"—chips designed from scratch for machine learning rather than adapted from graphics. Their BSP (Bulk Synchronous Parallel) architecture and massive on-chip SRAM offered a radically different approach to AI compute.
900 MB DISTRIBUTED SRAM
IPU Architecture
Bulk Synchronous Parallel for machine intelligence
Bulk Synchronous Parallel (BSP)
Unlike GPUs' SIMD model, the IPU uses BSP—each tile runs independently, then synchronizes at defined barriers. This enables irregular, sparse computations that GPUs struggle with. Perfect for dynamic neural network shapes and attention mechanisms.
Massive On-Chip SRAM
900MB of distributed SRAM across tiles—far more than any GPU. Model weights can live entirely on-chip, eliminating the memory bandwidth bottleneck. Each tile has its own local memory, creating a distributed computing fabric.
1,472 Independent Tiles
Each tile is a complete processor with 6 threads, local SRAM, and full instruction set. Tiles communicate via a high-bandwidth exchange fabric. This MIMD architecture handles sparse and dynamic workloads that trip up SIMD designs.
IPU-Fabric Scaling
IPUs connect via IPU-Links and IPU-Fabric for scale-out. A "POD" combines multiple IPUs with high-bandwidth interconnect. POD256 systems deliver petaFLOP-scale compute with unified memory model across chips.
Bow IPU Specifications
Third-generation Intelligence Processing Unit
Company Timeline
From Bristol startup to SoftBank acquisition
Strategic Analysis
What went wrong—and what might be salvaged
✦ Technical Strengths
- BSP architecture excels at sparse, irregular workloads
- 900MB on-chip SRAM eliminates memory bottleneck for small models
- MIMD design handles dynamic shapes better than GPUs
- Strong in GNNs, sparse neural networks, scientific computing
- Poplar software stack is well-regarded
- 3D wafer stacking was genuine innovation
⚠ Why It Struggled
- LLMs are dense, regular—the opposite of IPU's strengths
- 900MB SRAM insufficient for large transformer models
- No HBM meant couldn't compete for LLM inference
- CUDA ecosystem lock-in proved nearly unbreakable
- Market timing: sparse models never took over as expected
- Couldn't raise enough capital to iterate through architecture changes
◎ Under SoftBank
- SoftBank has deep pockets for continued development
- Potential synergies with Arm (SoftBank-owned)
- May pivot to edge AI or specialized applications
- UK team and IP remain valuable assets
- Could be combined with other SoftBank AI investments
- Acquisition price suggests technology still has value
⟁ Lessons Learned
- Betting on sparse AI was reasonable but didn't pan out
- $730M+ wasn't enough to compete with NVIDIA's R&D
- Software ecosystem matters as much as hardware
- Architecture designed for one workload is risky
- European AI chips face structural funding disadvantages
- Even great technology can't overcome ecosystem lock-in