TENSTORRENT
TENSIX // RISC-V AI Accelerator
The open-source challenger. Led by Jim Keller—the architect behind AMD Zen, Apple A-series, and Tesla's FSD chip—Tenstorrent is building customizable AI hardware on RISC-V. Their strategy: avoid expensive HBM, embrace standard DDR memory, and give customers the freedom to modify their chips.
CORE 120 Cores
CORE 120 Cores
CORE 120 Cores
CORE 120 Cores
HOST Control
CORE 120 Cores
CORE 120 Cores
CORE 120 Cores
CORE 120 Cores
The Legend Behind the Chips
Jim Keller is arguably the most influential microprocessor architect of the modern era. His track record of transformative chip designs spans four decades and multiple companies. When Keller joins a company, the industry pays attention—and when he became CEO of Tenstorrent, it signaled that this startup was serious about challenging NVIDIA.
Tensix Architecture
Open-source AI accelerator design
Tensix Cores
Each Tensix Core includes an array math unit for tensor operations, a SIMD unit for vector operations, and five RISC-V processors to manage data flow. Up to 120 cores per chip with 1MB SRAM each.
Network-on-Chip (NoC)
Proprietary 2D mesh interconnect moves data core-to-core and chip-to-chip. Enables efficient scaling without the complexity of traditional interconnects.
DDR Memory Strategy
"You can't beat NVIDIA if you use HBM" — Jim Keller. Tenstorrent uses standard DDR memory, avoiding supply chain constraints and reducing costs dramatically.
RISC-V Foundation
Open instruction set eliminates licensing fees and enables customer modifications. Part of Tenstorrent's broader vision for open AI hardware.
Metalium Software
Open-source software stack supporting PyTorch and JAX natively. Designed for transparency—no black-box compiler magic.
Chiplet Flexibility
Modular design allows mixing Tensix AI cores with custom I/O or memory chiplets. "Innovation License" lets customers modify core logic.
Product Portfolio
From edge to data center
Tenstorrent's first Tensix processor. Entry point for developers with up to 120 Tensix cores, 8GB LPDDR4 memory, and support for common AI precision formats (FP8, FP16, BF16).
Scalable data center chip with enhanced Ethernet connectivity for multi-chip configurations. Designed for both training and inference at scale.
High-performance RISC-V CPU core designed to compete with ARM. "Innovation License" allows customers to modify internal logic—unprecedented in the industry.
Successor to Ascalon targeting significant IPC improvements. Part of 18-month release cadence commitment.
Company Timeline
Building the open AI hardware ecosystem
Strategic Analysis
The open-source bet on AI hardware
✦ Competitive Advantages
- Jim Keller's reputation attracts top engineering talent
- RISC-V avoids ARM licensing fees and restrictions
- DDR memory strategy avoids HBM supply constraints
- Open-source approach appeals to enterprises wanting control
- IP licensing creates recurring revenue beyond chip sales
- Strategic investors (Samsung, LG, Hyundai) provide ecosystem
⚠ Key Risks
- NVIDIA's CUDA ecosystem creates massive switching costs
- Performance gap vs. HBM-based systems for large models
- Open-source approach may limit differentiation
- Multiple product lines may dilute engineering focus
- Competing with ARM is a different battle than competing with NVIDIA
- Two-year chip cadence is slower than hyperscaler pace
◎ Market Position
- Unique positioning: open architecture vs. proprietary competitors
- Strong in automotive (Hyundai, LG) and edge AI markets
- Samsung partnership provides manufacturing advantage
- Targeting customers who want hardware customization
- Ascalon could disrupt ARM's dominance in mobile/edge
- Taiwan presence strengthens supply chain relationships
⟁ Investment Thesis
- Jim Keller track record justifies premium valuation
- Dual revenue model: chips + IP licensing diversifies risk
- RISC-V momentum growing across industry
- Strategic investors unlikely to let company fail
- Could be acquisition target for hyperscaler wanting AI silicon
- Open approach may win as market matures past CUDA lock-in