F.1 CXL Protocol Types
| Protocol | Direction | Purpose |
|---|
| CXL.io | Bidirectional | PCIe-equivalent I/O, config, interrupts |
| CXL.cache | Device → Host | Device caches host memory |
| CXL.mem | Host → Device | Host accesses device memory (our primary) |
F.2 CXL.mem Latency Breakdown
| Component | Latency |
|---|
| Host controller | 10-20 ns |
| PCIe PHY (×16 Gen5) | 20 ns |
| Switch traversal | 50 ns |
| Endpoint controller | 30-50 ns |
| DRAM access | 80-100 ns |
| Return path | ~70 ns |
| Total | ~250 ns |
F.3 CXL vs PCIe DMA
| Aspect | CXL.mem | PCIe DMA |
|---|
| Latency | 250 ns | 5-10 μs |
| CPU involvement | None | Required |
| Semantics | Load/Store | Explicit DMA |
| Coherence | Hardware | Software |
Result: 40× latency improvement