Figure: the bandwidth-compute gap that starves modern AI infrastructure, in six stacked panels. An NVIDIA B200 supplies 2,250 TFLOPS of dense BF16 compute, 8 TB/s of HBM3e bandwidth and 192 GB of capacity, which means it needs an arithmetic intensity of 281 FLOPs per byte to stay busy, and transformer attention, dominated by KV-cache reads, delivers far fewer. Llama-70B costs 320 kibibytes per token, so an 8K context is 2.50 gibibytes, a 128K context is 40.0 gibibytes or about 43 gigabytes at batch 1 and 1.38 terabytes at batch 32, and a 4K context is 1.3 gigabytes at batch 1 and 43 gigabytes at batch 32; for a single sequence the KV only exceeds the weights at about 427,000 tokens. That opens two walls: a capacity wall of 1,376 gigabytes divided by 192 gigabytes, or 7.2 times, and a bandwidth wall of 8,000 gigabytes per second of HBM against 51 gigabytes per second of link-level PCIe Gen5 by 16, or 157 times. Reading one user’s 43 gigabyte cache therefore takes 5.4 milliseconds from HBM but 843 milliseconds over PCIe at that link-level rate, idling the GPU for 1,897 times 10 to the 12th wasted FLOPs. Real hardware data has since replaced the estimates this figure used to carry. On a DGX Spark GB10 measured on 19 August 2026 with Qwen2.5-7B in fp16, achieved streaming bandwidth is 236.5 gigabytes per second, which is 87 percent of the 273 gigabyte per second spec. That retires the roughly 50 percent effective-bandwidth haircut used in earlier drafts, and it withdraws the 16.4 gigabyte per second contended host-DRAM offload baseline this figure previously assumed, because the class of pessimistic estimate that baseline belonged to proved unreliable. Decode time is also two-term rather than one-term: t equals 100.3 plus 16.34 times KV in gibibytes for HuggingFace with SDPA at R squared 0.991, and t equals 73.9 plus 17.58 times KV in gibibytes for vLLM with FlashAttention-2 at R squared 0.945, giving inferred fixed-path bandwidths of 151.5 and 205.7 gigabytes per second against inferred KV-path bandwidths of 65.7 and 61.1. Under that fit the KV path is about 3.4 times more costly per byte, a model-derived ratio rather than a direct byte-level hardware measurement, and kernel substitution alone did not remove the KV slope, which stayed within 8 percent across the two frameworks. Four claims this figure used to make are retracted: the 15.6 times time-to-first-token result, because it rested on the withdrawn 16.4 gigabyte per second baseline; the 16 times user-capacity headline, because it was downstream of a 97 percent hit rate that was never measured; the 65 times access-latency headline of 13.0 microseconds of PCIe DMA against 200 nanoseconds of CXL.mem, because no CXL hardware was measured; and the 36 percent CapEx reduction, because it priced a configuration justified by the 16 times. No replacement cost figure is offered. The point that survives is that the GPU does not lack compute, it lacks data.

The Bandwidth-Compute Gap

Why Modern AI Infrastructure Starves for Data

Measured — DGX Spark GB10 Analytical model Vendor specification
NVIDIA B200
Compute (BF16/FP16 Dense)
2,250
TFLOPS
HBM3e Bandwidth
8
TB/s
HBM Capacity
192
GB
THE PROBLEM: Attention is Memory-Bound

Transformer attention: dominated by KV-cache reads

Few FLOPs per byte loaded → GPU waits for data
Llama-70B KV-Cache Size
2 (K,V) × 80 layers × 8 KV-heads × 128 dim × 2 B (BF16) = 320 KiB/token × seq_len × batch
128K Context
Batch 1
43 GB
Batch 32
1.38 TB
4K Context
Batch 1
1.3 GB
Batch 32
43 GB
This arithmetic is what stands, and it is where the retracted 16× user-capacity headline used to sit. 16× was downstream of a 97% HBM hit rate that was never measured, and under dense attention every block of an active sequence is read every step, so there is no small resident subset to serve 16 users from. It is withdrawn with no replacement claim. What survives is the capacity arithmetic itself, which never depended on any hit rate: 320 KiB/token for Llama-3 70B GQA (80 layers, 8 KV heads, head_dim 128, fp16), so 2.50 GiB at 8K and 40.0 GiB at 128K, and for a single sequence the KV only overtakes the 130.4 GiB of weights at a crossover of about 427,000 tokens. Concurrency is stated as KV-only capacity arithmetic, never as a served-user count.
CAPACITY WALL
KV-Cache (Batch 32 @128K)
1,376 GB
÷
B200 HBM3e Capacity
192 GB
Working set exceeds on-chip memory by
7.2×
32 × 43 GB = 1,376 GB — arithmetic over stated capacities, which is why it stands. The 16× user-capacity headline that used to be contrasted here is retracted; it came from a 37 GB hot set justified by a 97% hit rate that was never measured.
BANDWIDTH WALL
B200 HBM3e Bandwidth
8,000 GB/s
÷
PCIe Gen5 ×16 link-level
51 GB/s
Off-chip streaming-bandwidth penalty
157×
A bulk-bandwidth ratio over vendor specifications. The 65× access-latency headline (13.0 µs PCIe DMA ÷ 200 ns CXL.mem) that used to be contrasted here is retracted — no CXL hardware was measured, and the 200 ns access is demoted to an assumption inside a 32–121 GB/s range.
LATENCY IMPACT: 43 GB KV-Cache Read (one user @128K)
The 16.4 GB/s offload baseline is withdrawn — and so is the 15.6× TTFT built on it

This page uses 51 GB/s, the link-level uncontended PCIe Gen5 ×16 rate (Vendor specification): the raw signalling rate is 32 GT/s × 16 lanes ≈ 63 GB/s per direction, and ~51 GB/s is what survives 128b/130b encoding, TLP/DLLP headers and flow-control credit turnaround when nothing else is using the link. It makes the 157× ratio above an optimistic bound.

Earlier versions of this figure also carried a 16.4 GB/s contended end-to-end baseline, and derived a 15.6× TTFT result from it (43 GB ÷ 16.4 GB/s = 2,619 ms). Both are retracted. The 16.4 GB/s figure was an undefended estimate — a pessimistic haircut applied by convention rather than measurement — and the first real measurement on this package's hardware shows that class of estimate is unreliable. Baselines must be measured, not estimated. No replacement contention factor is offered, and no TTFT speedup is claimed.

Measured — DGX Spark GB10, 19 Aug 2026, Qwen2.5-7B fp16

Achieved streaming bandwidth is 236.5 GB/s = 87% of the 273 GB/s spec (streaming copy, 4 GiB buffers, median of 20). This retires the ~50% "effective bandwidth" haircut used throughout earlier drafts — the haircut was wrong, and wrong in the pessimistic direction, which is why it survived unexamined.

And decode time is two-term, not one-term: t = 100.3 + 16.34·KV_GiB (HF + SDPA, R² 0.991) and t = 73.9 + 17.58·KV_GiB (vLLM + FA2, R² 0.945). That gives an inferred fixed-path bandwidth of 151.5 / 205.7 GB/s against an inferred KV-path bandwidth of 65.7 / 61.1 GB/s: under that fit the KV path is ~3.4× more costly per byte, a model-derived ratio, not a direct byte-level hardware measurement. Kernel substitution alone did not remove the KV slope — it stayed within 8% across two frameworks with different attention implementations and paged vs unpaged layout, while the inferred fixed-path bandwidth improved 34% between them.

236.5 GB/s
Achieved streaming bandwidth — 87% of spec
65.7 / 61.1
Inferred KV-path GB/s (HF / vLLM)
151.5 / 205.7
Inferred fixed-path GB/s (HF / vLLM)
~3.4×
Cost of a KV byte against a fixed-path byte, model-derived
Also retracted on this page: the 36% CapEx reduction ($160,000 → $103,000), because it priced a configuration justified by the 16×. No cost model is restated, and no new cost figure is invented in its place. Capacity was in any case not the binding constraint in any configuration actually measured: everything fit in 128 GiB, and throughput still fell from 150 tok/s at batch 16 × 4K to 46 tok/s at batch 16 × 16K with memory to spare and nothing evicted.
THE BOTTLENECK
The GPU doesn't lack compute. It lacks data.
The capacity gap (7.2× at batch 32) forces off-chip storage. The bandwidth gap (157×) makes naive off-chip streaming catastrophic. A memory tier does not eliminate the KV memory wall — it changes its shape, from a capacity wall into a data-movement wall.
Sources
B200 specs: NVIDIA Datasheet (vendor specification) | Llama-70B: NVIDIA NeMo / Meta
PCIe Gen5 ×16 link-level 51 GB/s: PCI-SIG Base Specification 5.0 signalling rate less encoding and protocol overhead (vendor specification).
Bandwidth and decode-model figures: measured on a DGX Spark (GB10), 19 Aug 2026, Qwen2.5-7B-Instruct fp16 — scripts/bw_wall.py, scripts/vllm_slope.py; full method and raw tables in Appendix L.
Everything else derived on this page is an analytical model over vendor specifications, not a measured result. The 16.4 GB/s contended baseline, the 15.6× TTFT, the 16× user capacity, the 65× access latency and the 36% CapEx reduction are all retracted — see RETRACTIONS.