Distributed Endpoint Architecture

CXL 3.0 Type-3 Memory-Compute Node

HOST (CPU/GPU)
Load/Store Instructions
PCIe 5.0 x8/x16
ENDPOINT PACKAGE (UCIe Integrated)
CXL PROTOCOL ENGINE
CXL.mem
HDM-D/HDM-DB
CXL.io
Mailbox/Config
CXL.cache
Coherency
UCIe 1.1 — 1+ TB/s Die-to-Die
MEMORY CONTROLLER
CH 0-3
DDR5-6400
CH 4-7
DDR5-6400
8ch × 51.2 GB/s = 409.6 GB/s
COMPUTE CHIPLET
Core 0-3
A78 @ 3GHz
Core 4-7
A78 @ 3GHz
L3 Cache — 8 MB
CONTROL & MONITOR
Policy Engine
Access Tracker
Prefetch Queue
On-Package eSRAM
64 MB @ 8ns — Metadata & Index Storage
NVMe Controller
PCIe 4.0 x4 to Flash
DDR5 DRAM
256-512 GB
8× DDR5-6400 DIMMs
NVMe Flash
4-16 TB
Cold Tier Storage
DATA FLOW LEGEND
CXL.mem (Data)
CXL.io (Control)
UCIe (Internal)
DDR5 (Memory)
BANDWIDTH HIERARCHY
UCIe Internal
1+ TB/s
DDR5 Local
409.6 GB/s
CXL External
32-64 GB/s
NVMe Flash
~14 GB/s