Figure: the internal architecture of one CXL 3.0 Type-3 memory-compute endpoint, one of four identical units. A host CPU or GPU issues load and store instructions over PCIe 5.0 x8 or x16 into the endpoint package, where a CXL protocol engine terminates CXL.mem for HDM-D and HDM-DB, CXL.io for mailbox and configuration, and CXL.cache for coherency. A UCIe 1.1 die-to-die link carrying over 1 TB/s joins three chiplets: a memory controller driving 8 DDR5-5600 channels at 44.8 GB/s each for 358.4 GB/s, a compute chiplet of 8 Cortex-A78 cores at 3 GHz with 8 MB of L3, and a control and monitor block holding the policy engine, access tracker and prefetch queue. Alongside them sit 64 MB of on-package eSRAM at 8 nanoseconds for metadata and index storage, and an NVMe controller on PCIe 4.0 x4. Externally the endpoint attaches 256 GB of DDR5 across 8 DIMMs and 4 TB of NVMe flash as the cold tier. The bandwidth hierarchy falls from over 1 TB/s inside the package, to 358.4 GB/s of local DDR5, to 64 GB/s across the external CXL link, to about 14 GB/s of flash. Four such endpoints give 1 TB of DRAM at 200 nanoseconds, 16 TB of flash at 25 microseconds and 256 GB/s aggregate, at $5,000 per endpoint. All values are an analytical model, not measured.
CXL 3.0 Type-3 Memory-Compute Node
One of 4 identical endpoints: 256 GB DDR5 @ 200 ns and 4 TB NVMe @ 25 µs each, 64 GB/s each
(1 TB DRAM, 16 TB flash, 256 GB/s aggregate). Endpoint unit cost $5,000.
Analytical model — component specifications and derived bandwidths are modeled, not measured.