Figure: a step-by-step comparison of two modelled memory access paths for the same 4 kibibyte read. Both are component budgets assembled from vendor specifications and protocol behaviour; neither was measured, and no CXL hardware was measured anywhere in this package, so the ratio between them is not claimed and the previously published 65 times headline is retracted. The PCIe DMA baseline budget sums to 13.00 microseconds in seven steps: 4.00 microseconds driver call and doorbell, 2.50 DMA descriptor fetch, 1.50 software TLB and pinning, 0.70 PCIe Gen5 round trip, 0.10 host DRAM access, 0.20 payload transfer and 4.00 completion interrupt and resync. The CXL.mem direct budget sums to 200 nanoseconds in six steps: 15 nanoseconds request issue, 20 PCIe Gen5 by 16 PHY, 25 switch traversal, 40 endpoint controller decode, 80 DDR5-5600 array access and 20 return path. That 200 nanosecond figure is itself demoted to an unmeasured assumption inside a 32 to 121 gigabyte per second bandwidth range. The comparison bars below no longer rank per-access latencies against each other. They show what the argument actually uses, which is the time to move one whole 5.00 mebibyte block, that being 16 tokens at 320 kibibytes per token: 43 microseconds at an assumed 121 gigabytes per second, 82 microseconds at 64, and 164 microseconds at 32, set against 9 to 18 milliseconds of forward compute to regenerate the same 16 tokens at 50, 40 and 25 percent model FLOPs utilisation. Moving a block is two to three orders of magnitude cheaper than regenerating it, and no precise multiple is claimed. What the two waterfalls still show, and what does not depend on any ratio, is the shape of the difference: most of the PCIe cost is per-access driver and interrupt work that a load/store path never performs. The 177 nanosecond effective latency previously shown here is also retracted, along with the 97 percent hit rate it was computed from; the corrected simulation gives 8.5 to 91.6 percent depending on HBM budget, policy and workload, with LRU 38.34, LFU 16.09, EMA alpha 0.15 at 44.18 and EMA alpha 0.01 at 35.91 for a 32 gibibyte budget, and it is provisional rather than settled because a single data-structure defect in Revision 1 inverted four of five findings.

Memory Access Path Comparison

CXL.mem Direct Path vs CPU-Mediated PCIe Swap — both modelled, ratio not claimed

Analytical model Illustrative — component budget, unmeasured
PCIe DMA Baseline Path
13.00 µs

MODELLED · unmeasured assumption

1
Driver call + doorbell
Ring the device doorbell from the driver
4.00 µs
2
DMA descriptor fetch/setup
Descriptor allocation and fetch
2.50 µs
3
Software TLB + pinning management
Page pinning, IOMMU mapping
1.50 µs
4
PCIe Gen5 round trip
SerDes + switch, both directions
0.70 µs
5
Host DRAM access
DDR5 array read on the host
0.10 µs
6
4 KiB payload @ 32 GB/s
4,096 B ÷ 32 GB/s = 128 ns, rounded up for framing
0.20 µs
7
Completion interrupt + resync
MSI-X, handler, GPU resync
4.00 µs

4.00 + 2.50 + 1.50 + 0.70 + 0.10 + 0.20 + 4.00 = 13.00 µs

CXL.mem Direct Path
200 ns

MODELLED · unmeasured assumption, demoted to a 32–121 GB/s range

1
GPU/host request issue
Load instruction issued, M2S MemRd formed
15 ns
2
PCIe Gen5 ×16 PHY
SerDes transit, outbound
20 ns
3
CXL switch traversal
Non-blocking CXL 3.0 switch
25 ns
4
Endpoint CXL controller decode
HDM decode, address translation
40 ns
5
DDR5-5600 array access
Endpoint DRAM read
80 ns
6
Return path
Response through switch and PHY, writeback
20 ns

15 + 20 + 25 + 40 + 80 + 20 = 200 ns

What the argument actually costs: moving one 5.00 MiB block

The unit is a block, not an access: 16 tokens × 320 KiB/token = 5.00 MiB. Tier latency is an assumption across a 32–121 GB/s range, so the fetch cost is a range too.

Block fetch @ 121 GB/s
CXL 3.0 ×16 theoretical
Block fetch @ 64 GB/s
mid-range assumption
Block fetch @ 32 GB/s
pessimistic
Regenerate the same 16 tokens
off this scale

Bars are linear in µs on a 250 µs full scale; the regeneration bar is truncated because it runs two to three orders of magnitude past the fetch bars. Moving a block is two to three orders of magnitude cheaper than regenerating it — and that is the whole of the claim. No precise multiple is asserted: the two quantities do not measure the same operation, and an arbitrary interior block is not independently reproducible at all, because hidden states depend recursively on all preceding context. Forward compute for 16 tokens is 9 / 11 / 18 ms at 50% / 40% / 25% MFU.

43 µs
5.00 MiB @ 121 GB/s
82 µs
5.00 MiB @ 64 GB/s
164 µs
5.00 MiB @ 32 GB/s

Retracted from the earlier version of this figure: the 177 ns effective latency bar (0.97 × 100 ns + 0.027 × 200 ns + 0.003 × 25 µs) and the 65× badge on the PCIe row. The 97% HBM hit rate they rested on was never measured; the corrected simulation gives 8.5–91.6% depending on HBM budget, policy and workload — at 32 GiB, LRU 38.34, LFU 16.09, EMA α=0.15 44.18, EMA α=0.01 35.91. Those simulated values are Revision 2 and provisional: a single data-structure defect in Revision 1 inverted four of five findings.

Key Insight: CPU Elimination — a shape, not a ratio

A load/store path removes per-access CPU involvement in steady state: no interrupt, no context switch, no DMA setup. The GPU issues a load and receives data from endpoint DRAM through hardware-managed coherence. Control plane, mapping, faults, drivers and firmware still exist. That structural difference is what the two waterfalls show, and it does not depend on any ratio — which matters, because both budgets are modelled and no CXL hardware was measured. The 65× headline that used to sit here is retracted.

ratio
not claimed

Analytical model — every component latency here is modelled from vendor specifications and protocol behaviour. No hardware benchmark was run, and no CXL hardware was measured. Simulated hit rates quoted above are Revision 2 and provisional: a single data-structure defect in Revision 1 inverted four of five findings.