Figure: what a memory tier costs and what it actually buys. The effective-latency model this figure used to present is retracted in full. It computed L_eff as h_HBM times 100 nanoseconds plus h_CXL times 200 nanoseconds plus h_NVMe times 25 microseconds, worked it at a 97 / 2.7 / 0.3 hit split to get 177.4 nanoseconds, and reported 11.5 times lower end to end and 65 times lower per access. Every one of those numbers is withdrawn. The 97 percent HBM hit rate was never measured; there is no single hit rate to put in the formula. The corrected simulation, Revision 2, gives 8.5 to 91.6 percent depending on HBM budget, policy and workload, and at a 32 gibibyte budget the four policies give LRU 38.34, LFU 16.09, EMA alpha 0.15 at 44.18 and EMA alpha 0.01 at 35.91. Those values are provisional, not settled: a single data-structure defect in Revision 1 inverted four of five findings. The 200 nanosecond CXL access is demoted to an unmeasured assumption inside a 32 to 121 gigabyte per second range, and no CXL hardware was measured, so the 65 times ratio between the two modelled paths is not claimed. What replaces the model is the cost of moving a block against the cost of regenerating it. One block is 16 tokens at 320 kibibytes per token, which is 5.00 mebibytes; fetching it takes 164 microseconds at an assumed 32 gigabytes per second, 82 at 64 and 43 at 121, against 9 to 18 milliseconds of forward compute to regenerate the same 16 tokens at 50, 40 and 25 percent model FLOPs utilisation. Moving a block is two to three orders of magnitude cheaper than regenerating it, and no precise multiple is claimed, because the two quantities do not measure the same operation and an arbitrary interior block is not independently reproducible at all. The two path budgets are retained and both are labelled modelled: a PCIe DMA path summing to 13.00 microseconds and a CXL.mem load/store path summing to 200 nanoseconds, with the loaded-PCIe degradation ranges kept as illustrative. Real hardware data on a DGX Spark GB10 measured on 19 August 2026 with Qwen2.5-7B in fp16 is added: achieved streaming bandwidth of 236.5 gigabytes per second, which is 87 percent of the 273 gigabyte per second spec and retires the old roughly 50 percent effective-bandwidth haircut, and a two-term decode model, t equals 100.3 plus 16.34 times KV in gibibytes for HuggingFace with SDPA at R squared 0.991 and t equals 73.9 plus 17.58 times KV in gibibytes for vLLM with FlashAttention-2 at R squared 0.945, giving inferred fixed-path bandwidths of 151.5 and 205.7 gigabytes per second against inferred KV-path bandwidths of 65.7 and 61.1. Under that fit the KV path is about 3.4 times more costly per byte, a model-derived ratio rather than a direct byte-level hardware measurement, and kernel substitution alone did not remove the KV slope, which stayed within 8 percent across the two frameworks. Finally, the policy claims are corrected: alpha equals 0.2 was never validated, the simulated optimum is alpha of about 0.05 giving 55.96 percent at 32 gibibytes against LRU at 36.85 percent, which is plus 19.1 points, while at the specified alpha the margin over LRU is only plus 2.5 to plus 5.8 points, not plus 25. A decayed-frequency score is LRFU, published by Lee and colleagues at SIGMETRICS in 1999, and alpha is its documented knob between LRU and LFU behaviour, so the scoring function is established prior art and not a contribution.
Tier Cost Analysis
The effective-latency model is retracted. What the tier buys is the avoidance of regeneration — not a hit rate, and not a lower per-access latency.
The old formula is withdrawn. This card used to carry L_eff = h_HBM × L_HBM + h_CXL × L_CXL + h_NVMe × L_NVMe, worked at a 97 / 2.7 / 0.3 hit split to 177 ns. It cannot be worked at all, because there is no single hit rate to substitute: the corrected simulation gives 8.5–91.6% depending on HBM budget, policy and workload. What is left is a comparison the tier can actually win — moving a block against regenerating it.
ANALYTICAL MODEL · assumption
ANALYTICAL MODEL · assumption
ANALYTICAL MODEL · assumption
ANALYTICAL MODEL · linear term
That is the claim, and it is the whole of the claim. No precise multiple is asserted — the two quantities do not measure the same operation. The often-quoted 218× is one point in the range (17.9 ms ÷ 82 µs) and must always be quoted with its inputs. Regenerating an arbitrary interior block costs at least the forward-compute figure and potentially far more: interior KV is not independently reproducible, because hidden states depend recursively on all preceding context.
PCIe swap path latency components:
MODELLED · unmeasured assumption
MODELLED · demoted to a 32–121 GB/s range
Both budgets are component sums assembled from vendor specifications and protocol behaviour, measured across the same boundary (kernel issue → data available) with the same 4 KiB payload. Neither was measured, and no CXL hardware was measured anywhere in this package, so the 65× headline that used to sit here is retracted, along with the 11.5× end-to-end figure derived from it. The 200 ns access is demoted to an unmeasured assumption inside the 32–121 GB/s range used above. What the two budgets still show, and what depends on no ratio at all, is the shape: most of the PCIe cost is per-access driver and interrupt work that a load/store path never performs.
Illustrative magnitudes for a loaded driver-mediated path, not measurements and not inputs to any result below.
| Policy | Hit rate at 32 GiB | Margin over LRU |
|---|---|---|
| LRU | 38.34% | — |
| LFU | 16.09% | −22.3 pts |
| EMA α = 0.15 | 44.18% | +5.8 pts |
| EMA α = 0.01 | 35.91% | −2.4 pts |
Achieved streaming bandwidth is 236.5 GB/s = 87% of the 273 GB/s spec, which retires the old ~50% "effective bandwidth" haircut — the haircut was wrong, and wrong in the pessimistic direction. Decode time is two-term, not one-term: t = 100.3 + 16.34·KV_GiB (HF + SDPA, R² 0.991) and t = 73.9 + 17.58·KV_GiB (vLLM + FA2, R² 0.945). That gives an inferred fixed-path bandwidth of 151.5 / 205.7 GB/s against an inferred KV-path bandwidth of 65.7 / 61.1 GB/s: under that fit the KV path is ~3.4× more costly per byte, a model-derived ratio, not a direct byte-level hardware measurement. Kernel substitution alone did not remove the KV slope — it stayed within 8% across two frameworks with different attention implementations and paged vs unpaged layout.
α = 0.2 was never validated. The simulated optimum is α ≈ 0.05 — 55.96% at a 32 GiB budget against LRU's 36.85%, which is +19.1 pts. At the specified α the margin over LRU is only +2.5 to +5.8 pts, not the +25 pts previously claimed; that +25 was simply the endpoints of an additive ladder (72 → 80 → 87 → 93 → 97) for which no ablation was ever run. Quote each table against its own baseline: the +5.8 pts figure and the +19.1 pts figure come from different experiments with different LRU baselines and must not be mixed.
And the scoring function is not the contribution. A decayed-frequency score is LRFU (Lee et al., SIGMETRICS 1999) — established prior art — and α is its documented LRU↔LFU knob. What is claimed instead is a protocol result: make KV state and its control metadata a single migratable object, with identity-keyed policy state that survives the round trip between tiers. In simulation that persistence is worth more than the choice of policy (LFU +34.15 pts, EMA α = 0.01 +24.85 pts at 32 GiB), and it is testable with no CXL hardware.
Degradation figures above are illustrative ranges for a loaded PCIe path.
Path budgets and tier-fetch costs are an analytical model — no CXL hardware was measured. Hit rates are
simulated (provisional): Revision 2 of kv_tiering_sim_v2.py,
2–3 seeds, no hardware validation, and provisional because a single data-structure defect in Revision 1 inverted
four of five findings. Bandwidth figures are measured on a DGX Spark GB10, 19 Aug 2026,
scripts/bw_wall.py.