Chapter 4

Effective Latency Analysis

Two-tier cache model, CXL vs PCIe comparison, and the 65× latency improvement.

Figures in Chapter

250 ns

CXL.mem

16 μs

PCIe DMA

65×

Improvement

4.1 Two-Tier Cache Model

Tier	Media	Latency	Capacity
Tier 1	Endpoint DDR5	250 ns	1 TB
Tier 2	Endpoint NVMe	25 μs	16 TB
Fallback	Recompute	50 ms	∞

L_eff = α × L_dram + β × L_flash + γ × L_recompute Weighted average across cache tiers

With 85% DRAM hit rate, 14% flash hit, 1% miss:

Calculate:

L_eff = 0.85 × 250 ns + 0.14 × 25 μs + 0.01 × 50 ms

= 212.5 ns + 3.5 μs + 500 μs = 504 μs ≈ 0.5 ms

Figure 4.1 — Effective Latency Analysis Open Full Screen ↗

Figure 4.2 — Latency Path Comparison Open Full Screen ↗

Figure 4.3 — Latency Waterfall Diagram View TSX Source ↗

🚀 65× Latency Improvement

CXL.mem eliminates CPU interrupt handling, explicit DMA setup, and software TLB management. Result: 250 ns vs 16+ μs = 65× faster